[Trisquel-devel] RISCV T-Head CPU bug and Trisquel riscv64 port
Jing Luo
jing at jing.rocks
Fri Aug 9 05:47:20 UTC 2024
Hello all,
About two days ago, researchers published a sever CPU bug "ghostwrite"
in T-Head C910 and C920 CPU's vector extension. The CPU bug is
unpatchable by software, allows arbitrary memory write of *physical
address*. The only work around is to disable the vector extension in the
device tree (?), but with a significant performance penalty of 30~%.
https://ghostwriteattack.com/riscvuzz.pdf
I was going to buy the Milk-V Pioneer board (affected by the bug) and I
had plan to make it a pure build farm, running VMs for Trisquel and gcc
compile farm, etc. I even had it in my shopping cart, waiting for the
foreign exchange rate to drop so I could buy it. Now, I don't think it
is suitable for hosting anymore. I know Simon has one Pioneer board;
WDYT? Can someone else convince me "the bug is not that serious"?
I do have a Lichee Pi 4A (affected by this bug). Can I help with
Trisquel's riscv64 port? I can help build packages using sbuild, but
IIUC we need to bootstrap from a foreign distro first (Ubuntu) to get a
working schroot. Maybe I can help with that?
---
Anyways, since Simon asked about blobs on the gcc compile farm mailing
list, if I recommend some boards, I would recommend the mature and
reliable VisionFive 2 or the Pine Star64, both based on the same CPU
Starfive JH7110 which is not vulnerable to this bug. They are not really
as fast as T-Head C910, but they are inexpensive. You can buy like 5 of
them for a cluster. VisionFive 2 is already supported by mainline linux
(since 6.?), Star64 has support since 6.11-rc1, and the device tree can
be easily backported to 6.8 or 6.9. As for u-boot, AFAIK, u-boot itself
doesn't ship any blob. I have both of these boards, but I haven't
test/install them yet.
--
Jing Luo
About me: https://jing.rocks/about/
GPG Fingerprint: 4E09 8D19 00AA 3F72 1899 2614 09B3 316E 13A1 1EFC
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